Development of Digital Signal Processing Platform for Digital Hearing Aid

There has been a tremendous growth for the past few years in the field of VLSI and real time signal processing. Number of signal processing algorithms have been developed which allow the user to process real time signals such as speech to accomplish the signal with desired quality. Development of CMOS technology provides wide selection of low power FPGAs to be used in Digital system design. This paper introduces an efficient method to design a Digital Programmable Hearing Aid system working in association with Analog interface module. Real time signal processing algorithms such as Feedback and echo cancellation, Adaptive filtering , Dynamic range compression, Digital filter for decimation along with FFT and IFFT algorithms have been discussed using a 32 bit RISC processor core and hardware digital signal processing block, both residing in a Xilinx FPGA. Hardware configuration and software implementation are discussed in detail. Xilinx Spartan3, FPGA is used in system design. Spartan3 board has inbuilt ADC inside the chip so there is no need to use external CODEC system in design. Finally the challenges and the future work for additional improvement are discussed. KeywordsFPGA, RISC core, Xilinx ISE, FFT, IFFT, Adaptive filtering, Feedback cancellation DRC, Hearing threshold.